Intern, Logic Pathfinding Lab Advanced DTCO Engineer

1 Week ago • Upto 1 Years • Research & Development

Job Summary

Job Description

This internship in the Logic Pathfinding Lab focuses on Advanced Design Technology Co-Optimization (DTCO) for 2D and 3D ICs. Responsibilities include applying DTCO techniques using latest EDA tools, performing PPA analysis, customizing PDKs for 3D IC applications, and working on block-level physical design flows. The intern will analyze power and IR drop, propose new DTCO metrics, evaluate different DTCO methodologies, transfer advanced flows from Georgia Tech, and identify bottlenecks in technology. Collaboration with Samsung DTCO engineers is crucial, along with analyzing the impact of memory latency on system performance. The role requires working knowledge of standard cell design, library generation, place and route, and VLSI workload modeling.
Must have:
  • Graduate student in VLSI
  • DTCO experience (standard cell design, Place & Route)
  • VLSI workload modeling experience
  • Proficient in programming
Perks:
  • Relocation Support
  • Housing Stipend
  • Charitable Giving Match
  • Paid Therapy Sessions
  • Onsite Gym & Café
  • Flexible Environment

Job Details

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. 

Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Learn

  • Project Overview: Advanced Design Technology Co-Optimization for 2D and 3D IC
  • Skills You’ll Learn:
    • DTCO techniques including Place and Route using latest EDA tools
    • PPA analysis and interpretation
    • PDK customization for 3D IC applications

What You’ll Do

  • Block-level physical design flow for 2D and 3D ICs
  • Apply vector-based power and dynamic IR drop analysis for 2D IC reference circuits
  • Propose new or improve existing metrics for logic DTCO, considering workload and system level considerations

Location: Onsite at our San Jose headquarters 5 days a week

Reports to: Sr. Director

  • Evaluate pros and cons of different DTCO methodologies for 2D IC
  • Transfer advanced DTCO flow and examples from Georgia Tech, for 2D / 3D IC
  • Bring in relevant testcases from Georgia Tech – LPL collaboration for analysis and identify bottlenecks due to technology
  • Identify impact of memory (SRAM) latency and bandwidth on system level performance
  • Collaborate closely with Samsung DTCO engineers
  • Complete other responsibilities as assigned.

What You Bring

  • Graduate student enrolled in a Master or PhD program with academic focus in VLSI technology and design
  • Must have at least 1 academic quarter/semester remaining
  • Working experience on DTCO including standard cell design, library generation and characterization, and Place and Route
  • Working experience on VLSI workload modeling and the implications on the logic and packaging technologies
  • Proficient in programming
  • You’re inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

What We Offer
The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. 

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

Relocation Support Live 50+ miles away from your new office? No worries! We'll provide a stipend to help support your move.
Housing Stipend
Signing a lease on a new place for your summer internship? We'll help you pay your way with a monthly stipend.
Give Back
With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
Prioritize Emotional Wellness
With on-demand apps and paid therapy sessions, you’ll have support no matter where you are.
Stay Fit
Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
Embrace Flexibility
Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Hourly Base Pay Rate

$28 - $62 USD

Equal Opportunity Employment Policy 

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Recruiting Agency Policy

We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.

Covid-19 Policy

To help keep our employees, customers, and communities safe, we've developed guidelines for our team. Currently, we encourage vaccination for all employees and may require it depending on job functions (e.g., traveling for business, meeting with customers). While visiting our offices or attending team events, we ask employees to complete a daily health questionnaire and complete a weekly COVID test. Our COVID policies are subject to change depending on public health, regulatory, and business circumstances. 

Applicant Privacy Policy
https://semiconductor.samsung.com/us/careers/privacy

 

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