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Digital ASIC Micro Architect Design Engineer

Digital ASIC Micro Architect Design Engineer

2 Hours ago • 5 Years + • Research & Development

About the job

2 skills required for this role

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innovation

product-launch

Job Description

This role involves developing custom silicon solutions for Google's consumer products. Responsibilities include developing system Verilog RTL for ASIC/SoC products based on next-generation architecture specifications, performing digital design verification, defining hardware IP architecture specifications, and collaborating with SoC and system architects to meet power, performance, and area requirements for multimedia use cases. The ideal candidate will have 5+ years of experience in computer architecture, including microarchitecture, multimedia architecture, and silicon design, as well as experience in ASIC development methodology and Verilog RTL development. They will also collaborate with cross-functional teams including system and hardware architecture, IP design and verification, multimedia and machine learning algorithm and software development teams.

Must have:

System Verilog RTL development
Digital design verification
Hardware IP architecture definition
5+ years experience in computer architecture
ASIC development methodology
Collaboration with cross-functional teams

Good to have:

Master's or PhD in relevant field
Experience with low-power SoC hardware IP
Familiarity with interconnect or fabric, security, multi-level caching architectures

Perks:

Bonus
Equity
Benefits

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in computer architecture concepts, including microarchitecture, multimedia architecture, and silicon design.

Preferred qualifications:

Master's degree or Phd in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience architecting and designing low power SoC hardware IP in the following areas, (e.g.,Camera ISP, video codecs, display, computer cores and machine learning accelerators).
Experience in ASIC development methodology and require Verilog RTL development as per the project demands.
Experience in collaborating, cross-functionally with system and hardware architecture, IP design and verification, multi-media and machine learning algorithm and software development teams.
Familiarity with interconnect or fabric, security, multi-level caching architectures.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Develop system verilog RTL to implement reasoning for ASIC or SoC products according to next-generation architecture specifications.
Perform digital design verification of complex digital design blocks, and interact with architects to identify important verification scenarios.
Define and deliver the hardware IP architecture specifications that meet enaged power, performance, area and image quality targets, which will require owning the goals through to tape-out and product launch.
Collaborate with SoC and system architects on meeting dynamic power, performance and area requirements at the SoC level for multimedia use cases and experiences.

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$150.0K - $223.0K/yr (Outscal est.)

$186.5K/yr avg.

Worldwide

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.