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Staff Design Verification Engineer - CPU Subsystem

Karnataka, India (On-site)

Staff Design Verification Engineer - CPU Subsystem

3 Months ago • 2-5 Years • Research & Development • Undisclosed

About the job

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Job Description

Tenstorrent seeks a Staff Design Verification Engineer for their CPU Subsystem. You'll define verification plans, develop DV environments in SV/UVM, and execute test plans to ensure quality and reliability. Experience with System Verilog, UVM, and cache/NOC interconnect verification is essential.

Must have:

System Verilog
UVM Methodology
DV Experience
RTL Verification

Good to have:

Cache Verification
NOC Interconnect
AXI/CHI Protocols
C++ Knowledge

Perks:

Competitive Package
Equal Opportunity

About the job

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

This role is on-site, based out of Bangalore, India.

Responsibilities

Define verification plans and develop DV environments independently in System Verilog (SV)/UVM.

Knowledge of C++ is desirable.

Create and execute test plans to ensure the quality and reliability of our IP solutions.

Demonstrate expertise in System Verilog and UVM methodologies.

Perform functional verification at the RTL level, including coverage analysis and improvement.

Develop Universal Verification Components (UVCs) from scratch.

Experience with Cache, NOC Interconnect verification is desirable.

Knowledge of bus protocols like AXI, CHI etc. are added advantage.

Experience & Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

Proven experience in DV and verification methodologies.

Strong proficiency in System Verilog and UVM.

Ability to work independently and drive projects to completion.

Experience in IP development, particularly in DFD IP, is desirable.

Excellent problem-solving and communication skills.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

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