About the job
SummaryBy Outscal
RTL Design Verification Engineer with 3+ years of experience in Verilog/SystemVerilog and industry-standard verification methodologies (OVM/UVM). Strong understanding of ASIC design flow and verification techniques required. Excellent problem-solving and debugging skills.
About the job
๐๐จ๐ข๐ง ๐๐ฎ๐ซ ๐๐๐๐ฆ ๐๐ฌ ๐๐ง ๐๐๐ ๐๐๐ฌ๐ข๐ ๐ง ๐๐๐ซ๐ข๐๐ข๐๐๐ญ๐ข๐จ๐ง ๐๐ง๐ ๐ข๐ง๐๐๐ซ! at ARF Design
Are you passionate about RTL Design verification We're seeking a talented engineer to join our team and contribute to the semiconductor industry.
๐๐จ๐ฌ๐ข๐ญ๐ข๐จ๐ง: RTL Design verification Engineer
๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐: 5-10 Years
๐๐จ๐๐๐ญ๐ข๐จ๐ง: #Bangalore #Bhubaneswar #hyderabad
๐๐๐ฌ๐ฉ๐จ๐ง๐ฌ๐ข๐๐ข๐ฅ๐ข๐ญ๐ข๐๐ฌ::
Bachelor's or master's degree in electrical engineering/Electronics & Communication Engineering or related field.
๐๐ซ๐ข๐ฆ๐๐ซ๐ฒ ๐๐๐ช๐ฎ๐ข๐ซ๐๐ฆ๐๐ง๐ญ๐ฌ::
If you're ready to take your career to the next level and contribute to groundbreaking projects, we want to hear from you!
๐๐ฅ๐๐๐ฌ๐ ๐ฌ๐ฎ๐๐ฆ๐ข๐ญ ๐ฒ๐จ๐ฎ๐ซ ๐ซ๐๐ฌ๐ฎ๐ฆ๐/๐๐ ๐ญ๐จ poojakarve@arf-design.com
๐๐จ๐ญ๐: Please name the file in the following format: Your Full
๐๐๐ฆ๐_ ๐๐๐ฌ๐ข๐ ๐ง๐๐ญ๐ข๐จ๐ง_ ๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐.
Skills: design,rtl design,design verification testing,.com,universal verification methodology (uvm),verilog,systemverilog
Are you passionate about RTL Design verification We're seeking a talented engineer to join our team and contribute to the semiconductor industry.
๐๐จ๐ฌ๐ข๐ญ๐ข๐จ๐ง: RTL Design verification Engineer
๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐: 5-10 Years
๐๐จ๐๐๐ญ๐ข๐จ๐ง: #Bangalore #Bhubaneswar #hyderabad
๐๐๐ฌ๐ฉ๐จ๐ง๐ฌ๐ข๐๐ข๐ฅ๐ข๐ญ๐ข๐๐ฌ::
- Develop and execute verification plans for complex RTL designs.
- Perform functional and performance verification of design blocks.
- Collaborate with cross-functional teams to ensure successful IP component integration.
- Contribute to enhancing verification methodologies and best practices.
Bachelor's or master's degree in electrical engineering/Electronics & Communication Engineering or related field.
๐๐ซ๐ข๐ฆ๐๐ซ๐ฒ ๐๐๐ช๐ฎ๐ข๐ซ๐๐ฆ๐๐ง๐ญ๐ฌ::
- Minimum of 3+ years of experience in RTL design verification.
- Proficiency in Verilog/ SystemVerilog and experience with industry-standard verification methodologies (OVM/UVM).
- Strong understanding of ASIC design flow and verification techniques.
- Excellent problem-solving and debugging skills.
- Experience with formal verification tools and methodologies.
- Familiarity with scripting languages (e.g., Python, Perl) for automation tasks.
- Knowledge of industry-standard protocols and interfaces (e.g., PCIe, AXI, AHB).
- Opportunities for professional growth and career advancement.
- Vibrant and inclusive work culture that values collaboration and innovation.
If you're ready to take your career to the next level and contribute to groundbreaking projects, we want to hear from you!
๐๐ฅ๐๐๐ฌ๐ ๐ฌ๐ฎ๐๐ฆ๐ข๐ญ ๐ฒ๐จ๐ฎ๐ซ ๐ซ๐๐ฌ๐ฎ๐ฆ๐/๐๐ ๐ญ๐จ poojakarve@arf-design.com
๐๐จ๐ญ๐: Please name the file in the following format: Your Full
๐๐๐ฆ๐_ ๐๐๐ฌ๐ข๐ ๐ง๐๐ญ๐ข๐จ๐ง_ ๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐.
Skills: design,rtl design,design verification testing,.com,universal verification methodology (uvm),verilog,systemverilog
About The Company
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