Photonics Layout and Design Automation Engineer

About Us:

Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.

Role Summary:

We are looking for a Photonics design and layout automation engineer who will be a core part of silicon photonics circuit development. We are looking for technical expertise broadly across various areas including layout automation, PDK management, physical verification, and infrastructure management. The successful candidate will work to develop and deploy automation workflow and infrastructure for photonic integrated circuit designs and tape-outs.

• Drive and participate across various development activities including schematic driven layout and design, p-cell development, PDK management, and physical verifications
• Drive and participate in software selection procedures to implement integrated environment for photonics simulation and layout tools
• Participate in establishing a road map for photonics design automation
• Work cross-functionally with design, process and test teams to develop CAD infrastructure that facilitate the compliance of DfX requirements and foundry design rules
• Manage in-house photonic component model and layout libraries with proper revision control and regression tests.
• Continuously monitor quality escapes, and deploy corrective actions with a proper root cause analysis
  

• 5+ years of integrated circuit layout and design automation experience, preferably in a field of integrated photonics
• Comprehensive understanding of various areas of CAD developments encompassing simulation/layout automation, PDK development, and management, physical verification (LVS/DRC), hardware/software infrastructure management
• Expertise in p-cell development, LVS/DRC run-set development, source code revision control, and/or regression tests
• Proficiency in commercial software tools commonly used in photonics mask layout from Cadence, Synopsys, Luceda, and Klayout
• Familiarity with the semiconductor fabrication process
• Experience with source code and library management
• Experience with Python and Linux shell scripting
  

• Knowledge of silicon photonics, and optoelectronic device physics
• Familiarity with commercial photonics simulation software environments from Synopsys, Cadence, Luceda, and Ansys