Design Engineer Intern

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Silicon Solutions Group (SSG) develops industry-leading Digital IP (Intellectual Property), from RISC-V processor cores to DSPs to Memory Controllers and IO solutions. Our configurable and extensible IP solutions are poised to meet the demands of next-generation applications such as intelligent IoT Devices and ML/AI edge inference. All leading semiconductor providers can be counted as Cadence customers.

 
The Cadence SSG Team is hiring students to join our R&D teams in San Jose or Austin. This is an amazing opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. 
 

We aim to make you an integral part of the team by providing training, mentorship, and encouragement of your creative talents. Our goal is to equip students with practical work experience. We understand that it is best to learn by doing. We will provide tasks that enable you to learn while making meaningful technical contributions.

Be part of this great SSG Team where your contributions can make a visible impact. Your work will be integral to our success and the advancement of our industry.   
 

Description:

The student Intern will work with amazing talent on the team who are developing a wide range of advanced Digital IP’s spanning Neural IP, Network on Chip, CPU Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA for next generation of IP’s.

The Intern will also get an opportunity to work on designing IP’s on multiple generation of foundry technologies to deliver the best-in-class PPA for each technology node.

Position Requirements:

The student intern should have completed foundational coursework in Digital IC design, Computer Architecture and VLSI design. Exposure to VLSI design tools including Genus Synthesis, Innovus P&R and Tempus Static Timing Analysis flows is expected. The Intern needs to have proficiency in one or more programming languages including Tcl, Python, Perl & JavaScript.

• MS or PhD level program enrollment
• Background in RTL design including Verilog, synthesis, lint, formal.
• Strong communication skills
• Scripting language experience a plus

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