Senior Design Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure AI SOCs, cloud accelerators, cloud servers, and clients. 

We are looking for a Senior Design Verification Engineer  to work on leading edge IP (intellectual property) development as part of the SCIPS Semi-custom and Central IP (intellectual property) Silicon team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment. 

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. 

We are looking for a Senior Design Verification Engineer to join the team.

Required Qualifications: 

• 7+ years of related technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 5+ years of experience in design verification with a proven track record of full verification cycle on complex SoC IPs and/or systems.

• 5+ years experience with verification principles, testplan development, testbench creation, stimulus generation, Universal Verification Methodology (UVM) and coverage, debugging designs as well as creating simulation environments, with a proven track record of full verification cycle on complex SoC IPs and/or systems.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings

Microsoft Cloud Background Check

This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• In-depth knowledge of verification principles, testbenches, stimulus generation, UVM, and coverage.
• Substantial background in creating simulation environments, developing tests, and debugging designs.
• Solid understanding of chip and/or computer architecture.
• Scripting language such as Python, Ruby.
• Excellent communication skills.
• Energetic and self-motivated.
• Proven experience in two of more of the following would also be valuable:
  
  • Mixed Signal Design (Analog and Digital High speed links), IP and SOC level verification
  • Formal & Low Power

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until January 16, 2025.

As a Sr. Design Verification Engineer, you will be responsible for the following:

• Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom Intellectual Property (IP) components 
• Define pre-Si verification (simulation/emulation/formal proofs) and post-Silicon validation strategies 
• Work with a team to write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. 
• Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments. 
• Define and implement functional coverage and drive coverage closure. 
• Collaborate across verification teams on vertical and horizontal reuse of components. 
• Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Si testing is comprehensive 
• Write scripts for verification and validation infrastructure. 
• Apply Agile development methodologies using DevOps including code reviews, sprint planning, and feature deployment.
• Provide technical leadership through mentorship and teamwork.