Spring Co-Op, Mixed Signal Modeling & Verification (BO)

Cirrus Logic is seeking a creative and hardworking summer intern to join our outstanding Analog/Mixed-Signal Verification team. You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This position will play a vital role streamlining development methodology for our organization. You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs. Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS. Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design. Independent Interpretation of analog circuit schematics into abstract models. Collaborate with system architects and designers to streamline architectural exploration of next-generation IP. Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow. Collaborate with multi-functional teams to streamline chip-level integration. Performing regression debug support and other flow/infrastructure development.