Senior Photonic Layout Design Engineer

Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic Designs! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join our diverse team today!

What you'll be doing:

• The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers

• Conduct chip layout circuit design, circuit checking, and device evaluation and characterization.

• Responsible for chip floorplan, waveguide routing, photonic chip assembly, and back-end verification across multiple projects. Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools

• You'll work with Silicon Photonic and mixed-signal engineers to customize designs for integration in SiPh and other SERDES products

• Job duties will include floor planning, custom layout and verifying against design rules and schematics. Fill, post-processing, DRC mitigation, and foundry interactions

• Familiarity with Silicon Photonic and concept is strongly preferred.

What we need to see:

• BS in Electrical Engineering (or equivalent experience)

• At least 5+ years of hands-on layout design experience

• Deep understanding of analog circuit layout and Silicon Photonic concepts in CMOS and SiPhtechnologies. Validated experience with Cadence custom circuit design tools - particularly virtuoso

• Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield

• Ability to work optimally in a team, good interpersonal skills and positive energy.

• Proficiency in scripting languages like perl, python, skill etc. Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS