Senior Engineer Circuit Designer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi and Custom IP team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Engineer Circuit Designer to join the team

Required Qualifications:

• 7+ years of related technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, OR related field AND 4+ years technical engineering experience or internship experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 5+ years of experience in SRAM or Register file design

• 5+ years of experience in timing, power, EMIR characterization

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications: 

• Experience in SRAM and Register File design in advanced process technologies
• Understanding of SRAM write and read assist techniques
• Understanding of process technology and DTCO
• Understanding of layout and provide guidance to layout design
• Experience in yield and reliability
• Experience in providing technical guidance to other engineers and multitasking across multiple SoC programs
• Ability to concisely communicate design value propositions and risks
• Excellent debug skills

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until January 19, 2025. 
 

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• Collaborate with SoC designers to develop Memory SRAM and Register file solutions to difficult PPA challenges
• Work with internal and external process technology teams to understand and exploit advanced process DTCO knobs
• Devise methodologies for statistical analysis and timing/power/EMIR characterization
• Run quality assurance checks on IP collateral
• Develop IP and post-silicon characterization plans for inclusion on advanced process technology testchips
• Develop scripting automation for flows