Senior Design for Testability

We are seeking a skilled Design for Test (DFT) Engineer to join our dynamic team. The DFT Engineer will play a crucial role in ensuring the testability and manufacturability of our integrated circuits (ICs). The successful candidate will collaborate closely with the design, verification, and test teams to develop and implement DFT techniques that optimize test coverage and minimize test time.

Responsibilities:

1. Develop DFT architectures and methodologies for complex digital designs.

2. Define and implement scan insertion, ATPG (Automatic Test Pattern Generation), and BIST (Built-In Self-Test) structures.

3. Perform DFT simulations and analyses to ensure comprehensive test coverage and fault detection.

4. Collaborate with design and verification teams to incorporate DFT requirements early in the design cycle.

5. Work closely with the test engineering team to develop and debug test patterns for production testing.

6. Develop and maintain DFT scripts and tools to automate DFT tasks and improve productivity.

7. Support silicon bring-up and debug efforts by analyzing test results and diagnosing DFT-related issues.

8. Stay current with industry trends and advancements in DFT methodologies and tools.

Qualifications:

1. Min 4+ years of experience in DFT.

2. Bachelor's/Master's/Ph.D. degree in Electrical Engineering, Computer Engineering, or related field.

3. Experience with DFT techniques such as scan insertion, ATPG, BIST, and fault simulation.

4. Proficiency in scripting languages such as TCL, Perl, or Python for automation.

5. Familiarity with industry-standard EDA tools for DFT, such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Encounter Test.

6. Strong analytical and problem-solving skills.

7. Excellent communication and teamwork abilities.

8. Prior experience in ASIC or FPGA design is a plus.

9. Knowledge of analog/mixed-signal DFT techniques is desirable

10.Solid understanding of digital design concepts and methodologies.