ASIC Static Timing Analysis Engineer, Silicon

As an ASIC Static Timing Analysis Engineer at Google, you'll be responsible for driving sign-off timing convergence for high-performance designs. This involves setting up timing constraints, defining the overall STA methodology, and establishing the STA infrastructure and sign-off convergence flows. You'll collaborate with block owners to achieve sign-off timing convergence. The role requires extensive experience in silicon timing closure and chip integration, proficiency in STA tools (PrimeTime, Tempus, etc.), and expertise in constraint authoring for full-chip tape-out. You will contribute to the development of custom silicon solutions powering Google's direct-to-consumer products, impacting millions of users globally. The work involves pushing boundaries and shaping the next generation of hardware experiences.