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Synopsys Inc

A&MS Layout Design Engineer

Staff R&D Engineer

This role involves analog mixed-signal layout design and verification, with experience in high-speed SerDes IPs being a plus. Strong understanding of Deep submicron effects, CMOS and FinFET layouts, and ESD considerations are essential. Excellent communication skills are required for collaboration with internal teams.

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              About the job
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                  <span>      <ul><span><li>Experience in Analog Mixed-signal layout and verification , experience in high-speed SerDes IPs is a plus.</li></span><span><li><span class="white-space-pre"> </span>Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Floor-planning , Routing.</li></span><span><li><span class="white-space-pre"> </span>Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below.</li></span><span><li><span class="white-space-pre"> </span>Good understanding of basic ESD and latch-up layout design considerations.</li></span><span><li><span class="white-space-pre"> </span>Excellent written and verbal communication skills in interactions with internal development teams.</li></span></ul>
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