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ASIC Static Timing Analysis Engineer, Silicon

Karnataka, India (On-site)

ASIC Static Timing Analysis Engineer, Silicon

38 Minutes ago • 12 Years + • Research & Development

About the job

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Job Description

This role involves driving sign-off timing convergence for high-performance designs. Responsibilities include setting up timing constraints and the overall STA methodology, establishing the STA infrastructure and sign-off convergence flows, and collaborating with block owners for timing convergence. The ideal candidate will have 12+ years of experience in silicon timing closure and chip integration, expertise in STA sign-off constraint authoring, and experience with various static timing tools (PrimeTime, Tempus, etc.). The position contributes to the development of custom silicon solutions for Google's direct-to-consumer products, shaping next-generation hardware experiences.

Must have:

12+ years experience in silicon timing closure and chip integration
STA sign-off constraint authoring expertise
Experience with PrimeTime, Tempus, Timing Closure, STA tools
Drive timing convergence for high-performance designs
Set up STA infrastructure and sign-off flows

Good to have:

Master's degree in Electrical Engineering
Experience extracting design parameters and analyzing data trends
Knowledge of semiconductor device physics

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
12 years of experience in silicon timing closure and chip integration.
Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation.
Experience in one or more static timing tools: PrimeTime, Tempus, Timing Closure, STA, Timing ECO using Tweaker, Primeclosure, DMSA.

Preferred qualifications:

Master's degree in Electrical Engineering, or in a related technical field.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Knowledge of semiconductor device physics and transistor characteristics.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Drive the sign-off timing convergence for high performance designs.
Set up timing constraints, defining the overall Static Timing Analysis (STA) methodology.
Set up the STA infrastructure and sign-off convergence flows.
Work with block owners throughout the project for sign-off timing convergence.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.