Community

Home >

Jobs >

Senior Silicon Design Library Verification Engineer

Karnataka, India (On-site)

Senior Silicon Design Library Verification Engineer

1 Day ago • 6-8 Years • Research & Development • Undisclosed

About the job

3 skills required for this role

Add these skills to join the top 1% applicants for this job

front-end

quality-control

cad-computer-aided-design

Job Description

Microsoft seeks a Senior Silicon Design Library Verification Engineer to join its Central Front-End Tools, Flows, and Methodology (TFM) group. This role involves owning and maintaining Global Design/Verification Library components, managing releases to multiple SoC projects, providing leadership to the design community, and collaborating with stakeholders to define library design requirements. Responsibilities include developing and integrating common design and verification IP, working with EDA vendors, and mentoring junior team members. The ideal candidate will have extensive experience in front-end digital design and verification, Verilog/SV/UVM, and logic design compilation and simulation tools.

Must have:

6+ years Front-End Digital Design & Verification experience
Proficiency in Verilog/SV/UVM
Expertise in Design Compilation, Simulation tools
IP packaging, release, and qualification
Library component ownership and release management

Good to have:

MS in Electrical Engineering or related field
Experience with Standard cells, memories, behavioral modeling
Frontend qualification (lint, cdc, rdc, synth, low power)
IP design simulation debug flows
Understanding of existing IP functionality and connectivity

Perks:

Industry leading healthcare
Educational resources
Discounts on products and services
Savings and investments
Maternity and paternity leave
Generous time away
Giving programs
Networking opportunities

Overview

The Microsoft Silicon Engineering and Solutions Team is seeking passionate, driven and intellectually curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas like Global Design Libraries, RTL & VIP Design, Design Verification, Validation, Simulation/Debug, Coverage and SoC integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our Design/Verification engineers so that they can deliver cutting-edge silicon solutions for Microsoft.  

Qualifications

Required:   

BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience.

6+ years of experience in FrontEnd Digital Design and Verification.

Well-rounded and familiar with most Front-End Tools, Flows and Methodologies.

Strong Experience working with Verilog/SV/UVM based IP development.

Experience with Logic Design Compilation, Simulation tools and flows

Expertise in one of the following areas:

Design compile, elaboration and filelist/libraries handling.

IP packaging, release and qualification

IP integration

Additional Preferred:  

MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience.

8+ years of relevant experience.

Strong background in owning and maintaining design/verification IPs End to end and handling releases.

Good understanding with Standard cells, memories and behavioral modeling of design.

Hands on expertise getting an IP through Frontend qualification (lint, cdc, rdc, synth, low power..) and successful release.

Exposure to understand design functionality of existing IP, understand connectivity and apply incremental improvements.

Good background and exposure to FE VLSI design cycle.

Hands on experience working with IP Design simulation debug flows.

#SCHIEINDIA

Responsibilities

For all CAD roles, you will:   

Be part of a central FE CAD team that drives common FE methodologies for SoC and IP design. 
Be the expert in your domain and act in partnership with the execution team. 
Independently own, drive and maintain Global Design/Verification Library components and manage releases to multiple SoC projects.
Provide leadership to the design community for the CAD domain for which you are responsible. 
Work with stakeholders across the Microsoft Silicon group to collect library design requirements. 
Develop, enhance, and integrate common design and verification IP for organization-wide use.  
Work with EDA vendors to adopt the most optimal solutions for silicon verification and design. 
Mentor junior team members and summer interns.