Senior Network Design Verification Engineer, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
  
• 5 years of experience verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASIC.
• Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
• Experience in creating and using verification components and environments in standard verification methodology.

Preferred qualifications:

• Experience in verifying digital systems using standard Internet Protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
• Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.
• Experience with verification techniques, and the full verification life cycle.
  
• Experience with performance verification of ASICs and ASIC components.
  
• Experience with ASIC standard interfaces and memory system architecture.