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RTL Design Lead, Silicon

RTL Design Lead, Silicon

1 Month ago • 8-12 Years • Research & Development • Undisclosed

About the job

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Job Description

Lead a team delivering fabric interconnect IP, platforms, and subsystems. Drive multi-generation roadmaps for design optimization and define micro-architecture details. Oversee RTL development, debug simulations, and participate in synthesis, timing/power estimation, and silicon bring-up. Requires 8+ years of digital design in ASICs, 4+ years of people management, and expertise in RTL design using Verilog/SystemVerilog and microarchitecture. Experience with ARM-based SoCs, interconnects, and ASIC methodology is essential. The role contributes to the innovation behind Google's direct-to-consumer products, shaping the next generation of hardware experiences.

Must have:

8+ years ASIC digital design experience
4+ years people management
RTL design (Verilog/SystemVerilog)
ARM-based SoCs & ASIC methodology
Microarchitecture definition
Lead IP/SoC design team

Good to have:

Master's degree in EE/CE
Low power estimation & timing closure
Multi-generational IP/SoC roadmap experience

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital design in ASIC.
4 years of experience in people management.
Experience with RTL design using Verilog/System Verilog and microarchitecture.
Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

Master’s degree in Electrical Engineering or Computer Engineering.
Experience with methodologies for low power estimation, timing closure, and synthesis.
Experience leading IP/SoC design team for low power SoCs.
Ability to drive a multi-generational roadmap for IP/SoC development.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

Lead a team that delivers fabric interconnect IP, platforms, and subsystems.
Drive multi-generation roadmap for design optimization.
Define micro-architecture details (e.g., interface protocol, block diagram, data flow, pipelines, etc.).
Oversee RTL development, debug functional, and performance simulations.
Participate in synthesis, timing/power estimation, and Field-Programmable Gate Array/silicon bring-up.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.