Silicon Physical Design Engineer I

2 Months ago • 2 Years + • Research & Development

Job Summary

Job Description

This role involves managing block-level physical implementation and Quality of Results (QoR) on critical sensor IPs, developing and deploying low-power design methodologies, and reviewing Performance, Power, and Area trade-offs. Responsibilities include physical design methodology and flow validation/development, floor planning, physical design tool automation using PnR tools and scripting (Tcl/Perl/Shell/Python). The ideal candidate will have experience with synthesis to floor planning and Place and Route (PnR) bring-up with construction strategies. This position contributes to the innovation behind Google's hardware, delivering unparalleled performance, efficiency, and integration.
Must have:
  • Bachelor's degree in relevant field
  • 2+ years physical design experience
  • PnR tool experience & scripting (Tcl/Perl/Shell/Python)
  • Floor planning expertise
  • Manage block level physical implementation and QoR
Good to have:
  • Master's degree in relevant field
  • Experience with Innovus and Fusion Compiler
  • Low-power design methodologies
  • Synthesis to floor planning experience
  • PnR bring-up with construction strategies

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 2 years of experience with physical design methodology and flow validation/development methodology.
  • Experience in floor planning and physical design tool automation with PnR tools and scripting in Tcl/Perl/Shell/Python.

Preferred qualifications:

  • Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with Place and Route (PnR) tools (i.e., Innovus and Fusion Compiler) automations.
  • Experience with synthesis to floor planning, and Place and Route (PnR) bring-up with construction strategies.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Manage block level physical implementation and Quality of Results (QoR) on critical sensor IPs.
  • Develop and deploy low-power design methodologies.
  • Review Performance, Power and Area trade-offs in architecture, design, Register-Transfer Level (RTL) to Graphic Data System (GDS) flows.

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.

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