Principal DFT and Test Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell is looking for highly motivated, talented DFT and test development principal engineer. You will be part of a dynamic NPI product engineering team working on most advanced technologies in silicon process and SoC designs. Working at Marvell is fun, exciting and a lot of growth potential within the company. You will work closely with DFT, Design, Product, CAD, Firmware, and Reliability and Failure Analysis engineering teams to design, develop, and debug products as well as drive for design for testability solutions.

The Custom and Compute Business Unit at Marvell designs and develops industry leading SoCs for high core-count AI compute platforms, wired and wireless infrastructure, 5G and 6G acceleration silicon, custom ASIC designs for industry leading customers, and innovative storage technologies to address all segments of the hard disk drive (HDD) and solid-state drive (SSD) markets in cloud data centers, enterprises, and AI applications.

What You Can Expect

• As a Principal DFT and Test Engineer, you will be responsible for test program development for characterization, production, and wafer sort on Advantest 93K and/or Teradyne UltraFLEX tester platform(s)
• A Technical lead to drive the testability review with DFT/DFM teams to define and enhance yield and test methodologies
• Create all the documentation for detail test plans and test methodologies to meet product specifications
• Leading the efforts to work closely with DFT engineering team to ensure design verification of DFT IP inserted at RTL level and applying the right DFT methodologies in structure testing (ATPG/memory BIST)
• Test pattern conversion from design simulation environment to ATE format

What We're Looking For

• Bachelor’s degree in Electrical Engineering or related fields and 10- 15 years of related professional experience. Master’s degree and/or PhD in Electrical Engineering or related fields with 5-10 years of experience.
• Minimum 8+ years of test program development experiences on the Advantest 93K and/or Teradyne UltraFLEX ATE tester platform(s) with 3+ years of DFT related experiences
• Solid background in ATE testing (critical skill), test methodology, silicon process, DFT/DFM, and high-speed digital testing experience required
• Experience in one or more of the following is required: DFT including ATPG, memory BIST, design/DFT verification include simulation/timing closure, JTAG/ICL/PDL, functional test, high-speed IO
• Knowledge of ATPG pattern generation tool (such as Siemen Tessent Shell, Synopsys Tetramax), Scan/MBIST diagnostic (logical and physical layout aware), and DFT Insertion (Siemen Tessent Shell MBIST and BSCAN, Synopsys Design Compiler (DC))
• Strong knowledge of C/C++, Perl, Python, VCS, NC-Verilog, and Linux environment
• Must have effective interpersonal, teamwork, and communication skills
• Excellent problem solving, teamwork, collaboration and interpersonal skills
• Has an inherent sense of urgency and accountability
• Grounded, detail-oriented
• Must have the ability to multi-task in a fast-paced environment

Expected Base Pay Range (USD)

120,950 - 181,200, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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