Digital IC Design Engineer (Staff to Principal)

6578 Years ago • 10 Years + • Research & Development

About the job

Job Description

Marvell seeks a skilled Digital IC Design Engineer with 10+ years of experience in digital IP design. Responsibilities include RTL coding, verification, and collaboration with cross-functional teams. Strong knowledge of digital design methodologies, verification, and synthesis is essential.
Must have:
  • Digital IP Design
  • RTL Coding
  • Verification Methodology
  • Logic Synthesis
Good to have:
  • UVM Verification
  • Ethernet/DDR/SRAM
  • NVMe, NVMoF
  • ARM-based SoC
Perks:
  • Competitive Compensation
  • Great Benefits
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About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell is a leading provider of innovative storage technologies, including ultra-fast read channels, high-performance processors, leading-edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems.

Marvell Vietnam is one of Marvell's Research and Development (R&D) centers. We are seeking talented engineers to join our ASIC Development team and work with the most advanced technologies in IC design.

What You Can Expect

  • Work with IP/SoC architecture to study design feasibilities meeting PPA requirements.
  • Create Micro-architecture specification (MAS), perform RTL coding based on MAS using best RTL coding practices, and integrate the RTL into the IP/SoC.
  • Perform RTL code review, apply tools to formally check/fix RTL against various design rules.
  • Perform design verification for critically important design blocks.
  • Work with the verification team to define test-plan, debug/fix failures, analyze coverage.
  • Cooperate with Synthesis, DFT, STA, PnR teams to solve issues related to in-charged IP.
  • Support Emulation, FPGA prototype, functional ATE, and silicon validation teams.

What We're Looking For

  • BS/MS in Computer Science, Electrical Engineering, or related fields and 10+ years of related professional experience.
  • Proven track record of digital IP design from concept to successful ASIC/SoC project TOs.
  • Very familiar with digital IC design methodologies, understand all stages of ASIC design flows, and experienced with state-of-the-art design tools.
  • Hands-on behavioral and RTL coding experience, Verilog/SV preferred.
  • Strong knowledge of verification methodology, logic synthesis and timing analysis.
  • Excellent problem solving skills and out-of-the-box thinking to oversee design failures.
  • Very good at documentation and communication skills using English.
  • Experiences in UVM verification methodology is a plus
  • Experiences in Ethernet/DDR/SRAM/USB/PCIe/USB/SAS/SATA IF is a plus.
  • Experiences in NVMe, NVMoF, ARM-based SoC, Emulation, FPGA prototype is a plus.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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About The Company

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Pavia, Lombardy, Italy (On-Site)

Pavia, Lombardy, Italy (On-Site)

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Ho Chi Minh City, Ho Chi Minh City, Vietnam (On-Site)

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Irvine, California, United States (Hybrid)

Singapore (On-Site)

Santa Clara, California, United States (On-Site)

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