Physical Design Engineer

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Do you want to collaborate with the best minds in the world? Are you passionate about AI and its potential in transforming the future of computing? Join our world-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon and AI products.

Who You Are

Your job responsibilities will include but not limited to:

• Physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

• Analyzes results and makes recommendations to fix violations for current and future product architecture.

• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

• Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

• In addition to the skills listed above the ideal candidate will also have excellent communication, teamwork, and problem-solving skills. As well as a willingness to work independently at various levels of abstraction.

Qualifications

Minimum Qualifications

• Bachelor’s degree in electrical or computer engineering, or a related field with a year of related experience OR Master’s degree in electrical or computer engineering, or a related field.

• 1 year experience with CMOS transistor level circuit fundamentals

• 1 year experience with VLSI hardware design and program

Preferred Qualifications

6+ months of experience with:

• TL/Logic design Verilog, VCS, etc.

• Electronic Design Automation tools, flows and methodology

• Fusion Compiler, Primetime

• Layout cleanup expertise DRCs, density, etc.

• Circuit design

• Computer architecture

• TCL, Python, Perl and/or C++ programming

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Annual Salary Range for jobs which could be performed in the US $91,500.00-$137,436.00*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change...