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ASIC Design Engineer, Platform IP, Silicon

California, United States (On-site)

ASIC Design Engineer, Platform IP, Silicon

3 Weeks ago • 3-6 Years • Research & Development • $127,000 PA - $187,000 PA

About the job

5 skills required for this role

Add these skills to join the top 1% applicants for this job

algorithms

python

perl

fpga

innovation

Job Description

This ASIC Design Engineer role at Google involves developing custom silicon solutions for direct-to-consumer products. Responsibilities include defining microarchitecture details (interface protocol, block diagram, data flow, pipelines), RTL development (SystemVerilog), debugging simulations, performing RTL quality checks (Lint, CDC, Synthesis), participating in synthesis, timing/power estimation and FPGA/silicon bring-up, and collaborating with multi-disciplinary teams. The ideal candidate possesses experience in digital logic design, RTL design (Verilog/SystemVerilog), logic synthesis techniques, ARM-based SoCs, and scripting languages (Python/Perl). Experience with IP design, low-power techniques, and RTL quality checks is preferred.

Must have:

3+ years digital logic design experience
RTL design (Verilog/SystemVerilog)
Logic synthesis & low-power techniques
ARM-based SoC and ASIC methodology experience
Scripting (Python/Perl)
RTL quality checks (Lint, CDC)

Good to have:

Master's/PhD in relevant field
IP design experience (clocking, interconnects, peripherals)
Low power estimation, timing closure, synthesis methodologies
Experience with tools for RTL quality checks

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power design techniques.
Experience with ARM-based SoCs, interconnects and ASIC methodology.
Experience with a scripting language like Python or Perl.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
3 years of experience with Intellectual Property (IP) design for clocking, interconnects or peripherals.
Experience with methodologies for low power estimation, timing closure, or synthesis.
Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our team takes pride in our ability to transform algorithms and processes into a user-friendly form. If you are someone who enjoys crafting tools to empower other creative people then this is the right job for you.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
Perform RTL development (SystemVerilog), debug functional/performance simulations.
Perform RTL quality checks including Lint, Critical Dimension Control, Synthesis, Unified Power Format checks.
Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
Communicate and work with multi-disciplined and multi-site teams.

View Full Job Description

$127.0K - $187.0K/yr (Outscal est.)

$157.0K/yr avg.

Mountain View, California, United States

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.