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TPU RTL Design Engineer

TPU RTL Design Engineer

1 Hour ago • 3 Years + • Research & Development

About the job

2 skills required for this role

Test your skills to join the top 1% applicants for this job

innovation

cross-functional

Job Description

As a TPU RTL Design Engineer at Google, you'll be part of a team developing ASICs for data center computation acceleration. Responsibilities include microarchitecture specification creation and review, SystemVerilog RTL development for ASIC products, collaborating with DV teams on test plans, and working with Physical Design teams to ensure design requirements are met. You'll contribute to the design, architecture, documentation, and implementation of next-generation data center accelerators, directly impacting the performance and efficiency of Google's products used by millions.

Must have:

Bachelor's degree in relevant field
3+ years experience with IC development tools
3+ years SystemVerilog RTL design experience
Develop SystemVerilog RTL
Work with DV and Physical Design teams

Good to have:

Master's/PhD in relevant field
Cross-functional team experience
Computer architecture knowledge
Processor design, accelerator, or memory hierarchy knowledge

Perks:

Bonus
Equity
Benefits

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
3 years of experience with industry-standard tools used in the development of silicon-based ICs and chips.
3 years of experience with digital design using SystemVerilog RTL.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
Experience in interacting with software, architecture, and other cross-functional teams.
Experience applying computer architecture principles to solve problems.
Knowledge of the fundamentals of Computer Architecture.
Knowledge of processor design, accelerators, or memory hierarchies.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Tensor Processing Unit (TPU) RTL Design Engineer, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Work independently to create and review compute subsystem's design microarchitecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
Work with Physical Design teams to ensure design meets physical requirements and timing closure.

View Full Job Description

$127.0K - $187.0K/yr (Outscal est.)

$157.0K/yr avg.

Worldwide

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.