Principal Solutions Engineer: Physical Design - Implementation and Signoff

1 Month ago • All levels • Research & Development

About the job

Job Description

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Principal Solutions Engineer:  Physical Design - Implementation and Signoff to work with us in Brazil.

As a Principal Solutions Engineer:  Physical Design - Implementation and Signoff, you will be part of the Silicon Engineering team. In this role, you will work with an experienced Cadence team and leading-edge customers to implement SoC designs in advanced process nodes. You will use Cadence’s market-leading technologies in synthesis, place & route and signoff verification to help customers turn their design ideas into products that will be deployed in the marketplace.

Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

Job Description:

  • Perform the place and route flow of complex digital SoC IPs for customer technical needs;

  • Perform STA to ensure timing closure;

  • Perform the physical verification (DRC, LVS, IR Drop and EM) of complex digital SoC IPs;

  • Ensure that the design met all the requirements for power, performance and area;

  • Work closely to the Front-end team to validate the physical design deliveries such as the initial netlist and constraints and to guarantee that the design will be feasible;

  • Provide technical training to new team members.

Requirements:

  • Complete Bachelor’s degree in Computer/Electrical Engineering or related areas;

  • Strong knowledge of digital design and semiconductor fundamentals;

  • Expert in the place and route flow;

  • Strong knowledge in timing analysis and fixes;

  • Strong knowledge in IR Drop/EM analysis and cleanup;

  • Strong knowledge in DRC/LVS cleanup;

  • Strong verbal and written skills and collaboration capabilities;

  • Experience in scripting languages (Python, TCL).

Nice to have:

  • Past experience with SoCs tape-outs with advanced nodes;

  • Low power design and techniques;

  • Strong knowledge in Cadence’s physical design tools (Innovus, Tempus, Voltus, Pegasus);

  • Experience with Cadence’s synthesis tool (Genus).

Additional Job Details:

  • Employment category: CLT

  • Employment term: 40 hours/week.

  • Hybrid work.

  • Competitive benefits.

About Cadence:

Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.

For more information, access http://www.cadence.com

Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success

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We’re doing work that matters. Help us solve what others can’t.

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About The Company

Yokohama, Kanagawa, Japan (On-Site)

Feldkirchen, Bavaria, Germany (Hybrid)

San Jose, California, United States (On-Site)

San Jose, California, United States (On-Site)

Burlington, Massachusetts, United States (On-Site)

Katowice, Silesian Voivodeship, Poland (On-Site)

San Jose, California, United States (On-Site)

San Jose, California, United States (On-Site)

San Jose, California, United States (On-Site)

Bengaluru, Karnataka, India (On-Site)

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