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ASIC RTL Design Engineer, Machine Learning Accelerators

Wisconsin, United States (On-site)

ASIC RTL Design Engineer, Machine Learning Accelerators

1 Month ago • 2-4 Years • Research & Development

About the job

2 skills required for this role

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innovation

cross-functional

Job Description

As an ASIC RTL Design Engineer, you will be part of a team developing cutting-edge ASICs used to accelerate Machine Learning computation in Google's data centers. You will participate in the microarchitecture, design, documentation, and implementation of the next generation of Machine Learning center accelerators. You will work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications. You will also develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines. You will work with Design Validation (DV) teams to create testplans for, verify, and debug design RTL. You will also work with physical design teams to ensure design meets physical requirements and timing closure.

Must have:

Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
2 years of experience in Digital design using SystemVerilog RTL

Good to have:

Master's degree or PhD in Electrical Engineering or Computer Science.
4 years of experience in digital/ASIC design using SystemVerilog or RTL.
Experience in one or more successful ASIC products from concept to silicon.
Experience interacting with software, system hardware, and other cross-functional teams.
Experience defining SoC IP interfaces and methodologies.
Understanding in computer architecture/memory subsystem architecture.

Perks:

Bonus
Equity
Benefits

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
2 years of experience in Digital design using SystemVerilog RTL.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering or Computer Science.
4 years of experience in digital/ASIC design using SystemVerilog or RTL.
Experience in one or more successful ASIC products from concept to silicon.
Experience interacting with software, system hardware, and other cross-functional teams.
Experience defining SoC IP interfaces and methodologies.
Understanding in computer architecture/memory subsystem architecture.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing cutting-edge ASICs used to accelerate Machine Learning computation in Google's data centers. You will participate in the microarchitecture, design, documentation, and implementation of the next generation of Machine Learning center accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
Work with Design Validation (DV) teams to create testplans for, verify, and debug design RTL.
Work with physical design teams to ensure design meets physical requirements and timing closure.

View Full Job Description

$127.0K - $187.0K/yr (Outscal est.)

$157.0K/yr avg.

Madison, Wisconsin, United States

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.