Principal Digital Design Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Digital IC Design Principal Engineer at Marvell, you will join the pivotal Switching business group. This team plays a crucial role in Marvell’s success within the Datacenter and Infrastructure markets, driven by the AI boom. We collaborate closely with several Hyperscalers to develop switching solutions tailored for the cloud and AI sectors.

What You Can Expect

• Serve as the responsible engineer for at least one critical design block, including architecture definition, design specifications, and RTL delivery.

• Code and deliver high-quality RTL to the PD and DV teams.

• Collaborate with the Architecture team to define new features and suggest optimizations for power, latency, and performance.

• Work with the PD team to resolve timing violations, Spyglass warnings/errors, and CDC violations.

• Partner with the DV team to root-cause and fix design bugs.

• Lead root cause investigations, silicon validation bugs, and hardware correlation issues.

What We're Looking For

• Hold a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Degrees in mathematics, physics, or other sciences may be considered if you have completed adequate coursework in electronics or have gained relevant knowledge through work experience.

• Be proficient in coding System Verilog for complex design blocks.

• Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time.

• Have experience taking design blocks through the full design cycle, from micro-architecture to tapeout.

• Have experience with timing fixes, area and power optimizations, and resolving silicon issues.

Expected Base Pay Range (USD)

140,180 - 210,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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