Cognizant (Nasdaq-100: CTSH) engineers modern businesses. We help our clients modernize technology, reimagine processes and transform experiences so they can stay ahead in our fast-changing world. Together, we’re improving everyday life. See how at www.cognizant.com or @cognizant.

Cognizant

Oracle BRM CI-CD

Art Director - Manager

Hiring Polarion Lead Developer.

Reverse Engineer (Android) / Barcelona-based / hybrid)

Marvell

Design Engineering Intern (Master’s Degree)

Analog Design Engineer, Senior Principal

Analog Design Engineer, Staff

Analog Design Engineer, Senior Staff

Analog Designer junior

Analog Design junior

Staff Engineer, Analog Layout

Unity

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Developer, Release Tools, Release Engineering

Marvell seeks a Design Engineering Intern (Master's) to contribute to the development of next-generation high-speed PAM/Coherent DSPs and PHY designs. Responsibilities include performing digital design tasks using HDL, digital verification, DFT design, synthesis, static timing analysis, and power analysis; coding in TCL, Perl, Python, and Unix shell; optimizing and simulating high-speed parallel DSP architectures; analyzing parallel DSP optimization challenges; collaborating with cross-functional teams; and working in an international environment.  The ideal candidate will be a final-year Master's student (or recent graduate) in a relevant technical field from an accredited Italian university, possessing basic digital design knowledge and ideally some familiarity with design verification, DFT, and digital signal processing. Strong English communication is essential.

Analog Design Engineer

Facilities Commodity Manager

Hardware Board Design Principal Engineer

<div class="css-ey7qxc"><div data-automation-id="jobPostingDescription" class="css-dwylkc">About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.&nbsp;At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.&nbsp;Your Team, Your ImpactMarvell’s high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem, providing low-power, high-performance solutions for cloud data center infrastructure, service providers, AI networks, enterprises, and 5G. You will be part of a highly-skilled, dynamic team driving the development of Marvell’s next-generation high-speed PAM/Coherent DSPs and PHY designs, which utilize cutting-edge CMOS technology.What You Can Expect<ul><li>Perform digital design tasks using digital design and verification tools, including HDL design, digital verification, DFT design, synthesis, static timing analysis, and power analysis.</li><li>Code in scripting languages such as TCL, Perl, Python, and Unix shell.</li><li>Work on optimizing and simulating high-speed parallel DSP architectures.</li><li>Analyze and explore parallel DSP optimization challenges and solutions.</li><li>Collaborate with cross-functional teams (architecture, validation, software) to optimize device solutions.</li><li>Work in an international environment, engaging with teams across multiple locations.</li><li>Skills You’ll Learn:&nbsp;Advanced Parallel DSP and PHY Design, Cutting-edge Digital Design, Verification and DFT Techniques, and Static Timing Analysis Concepts—familiarity with the latest technologies. </li></ul>What We're Looking For<ul><li>Bachelor’s degree in Electrical Engineering, Software Engineering, or a related field.</li><li>Final-year Master’s student in Electronics, Software Engineering, Mathematics, Physics, or a similar technical field at an accredited Italian university or a recent master’s graduate (within the last 12 months).</li><li>Basic knowledge of digital design.</li><li>Basic knowledge of design verification and DFT (Design for Test) is a plus.</li><li>Knowledge of digital signal processing is a plus.</li><li>Strong written and verbal communication skills in English</li></ul>#LI-SJ1<h3></h3>Additional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our <a rel="noopener noreferrer" target="_blank" href="https://www.marvell.com/company/careers/">Careers</a> page.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.#LI-SJ1</div></div>

Oracle BRM System Test Lead with 8-12 years of experience. Must have expertise in BRM PDC, ECE, OCOMC, OC3C. Experience with BRM Cloud native implementation testing is required. Strong functional testing skills and test automation experience is a plus.

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 Job Summary Oracle BRM System Test Lead - Experience ranging from 8 to 12 years.Functional expertise with Oracle BRM PDC ECE OCOMC OC3C to derive test plan based on requirements developer test cases and execute system functional testing of Oracle BRM revenue management solution. Test tools and test automation experience is added advantage. Experience with BRM Cloud native implementation testing is required. E2E integration testing of BRM solution is added advantage. Lead system test team of 4 to 6 Team Responsibilities Oracle BRM 12 or above versions hands-on functional knowledge and system testing experience (onprem and cloud native versions). Certifications Required Oracle Billing and Revenue Management (BRM) Functional testing skills of BRM billing system.
 
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